The present invention relates to techniques of video signal processing, and more particularly to a method and circuit arrangement for video signal processing suitable for use with a display apparatus which displays an image of a video signal such as a television signal through enlargement and compression to an arbitrary picture size.
At the prevalence of a high-definition television system having an attribute of 16:9 aspect ratio, various studies are under way on the compatibility with the conventional standard television systems such as an NTSC system. Among several problems encountered in displaying a picture of the standard 4:3 aspect ratio on a display unit with a 16:9 aspect ratio, a specific problem is the difference of luminance decay of phosphor due to a side panel signal or side blank panel signal which is applied to the unused sections of the screen.
When the standard video signal of the 4:3 aspect ratio is displayed intact on a display unit with the 16:9 aspect ratio, a circular image turns to a horizontally elongated ellipsoidal image as shown in FIG. 3A, and generally, this impropriety is avoided by compressing the video signal in the horizontal direction as shown in FIG. 3B and displaying the resulting signal with side panel signals being inserted at the rightmost and leftmost sections of the screen as shown in FIG. 3B. However, this method does not use the wide screen area of 16:9 aspect ratio efficiently, i.e., it leaves the partial screen areas unused. In this respect, JP-A-3-11891 offers a method of using the whole screen area by display the standard video signal through the expansion in the vertical direction as shown in FIG. 3C.
FIG. 4A is a conceptual circuit diagram showing the circuit arrangement for carrying out the above-mentioned prior art. In the Figure, a reference numeral 401 denotes an input terminal for the NTSC television signal, 402 denotes an output terminal for the video signal with an attribute of converted aspect ratio, 403 denotes a NTSC decoder which separates the NTSC television signal into a luminance and color difference signal, 404 denotes a non-interlace conversion circuit which converts the signal into double-rated signal for progressive scanning, 405 denotes a first memory circuit used for the time base conversion, 406 denotes a second memory circuit used to determine the extracting position of the video signal, 407 denotes a line calculation circuit which implements the image calculation for an upper and lower lines on the screen, and 408 and 409 denote a first and second selection switching circuits.
In the case of displaying a picture of a 4:3 aspect ratio by inserting the side panel signals in the rightmost and leftmost sections of the screen as shown in FIG. 3B, the first memory circuit 405 is operated by application of a read clock which is higher than the write clock so as to compress the time axis, and the resulting video signal is supplied to the display unit through the a-contact of the second selection switching circuit 409. In the case of displaying a picture represented by a video signal which is derived from a NTSC television signal and conditioned to the 16:9 aspect ratio (the video signal is prerecorded as a "squeezed signal" in which a circular image is reformed in a vertically elongated ellipsoidal image as shown in FIG. 3D), the video signal is fed through intact by way of the a-contact of the first selection switching circuit 408 and the b-contact of the second selection switching circuit 409, instead of using the first and second memory circuits. In this case, the video signal can be displayed to produce a picture of accurate shape on the display screen with a 16:9 aspect ratio as shown in FIG. 3E. In another case of displaying a magnified picture by cutting off its top and bottom sections as shown in FIG. 3C, a second memory circuit 406 having a large storage capacity is used to define the extraction area of picture and the picture is expanded in the vertical direction based on an interpolation process by the line calculation circuit 407.
FIG. 4B shows the arrangement of the line calculation circuit 407. In the Figure, a reference numeral 410 denotes an input terminal for the video signal provided by the second memory circuit 406, 411 denotes an output terminal, 412 denotes a one-line delay memory circuit, 413 and 414 denote coefficient memories used to magnify the image of input signal at a fixed magnification factor, and 415 denotes an adder. The interpolation process implemented by the line calculation circuit 407 will be explained in detail in connection with FIG. 5.
Columns (A) and (B) in FIG. 5 show proper levels and weighting factors or coefficient of scanning lines in magnifying a picture by 4/3 in this example through the interpolation of scanning lines. The video signal for the 4/3 magnification can be produced through a relatively simple filtering process for the factors, as will be appreciated from the Figure. Column (C) in FIG. 5 shows scanning lines on the input terminal 410, i.e., the output of the field memory circuit 406, indicating that the same scanning line is read out once in every four lines. Column (D) in FIG. 5 shows values in the second coefficient multiplier 414 which stores coefficients .alpha. to be multiplied to the scanning lines on the input terminal 410. Column (E) in FIG. 5 shows output scanning lines provided by the one-line delay memory 412. Column (F) in FIG. 5 shows coefficients (1.alpha.) in the first coefficient multiplier 413. Column (G) in FIG. 5 shows output signals of the adder 415. By producing a new scanning line while switching the coefficient for each line, an expanded video signal image a picture having the correct levels shown by (B) in FIG. 5 is obtained. In this manner, the conventional system is devised to display properly an image or picture of a video signal with a 4:3 aspect ratio on a display unit with the 16:9 aspect ratio.
Another prior art disclosed in JP-A-3-60583 uses a deflection circuit for displaying a picture from a video signal of a movie picture size through the vertical expansion thereby to accomplish a display mode of FIG. 3C.
On the other hand, the technique for a display mode shown in FIG. 3B through the compression of input video signal in the horizontal direction is conventionally based on the formation of a read clock from the write clock of the first memory circuit 405 by use of phase locked loop (PLL) circuits. However, such method necessitates multiple PLL circuits within a synchronizing system (sync system) including a PLL circuit for producing the read clock, a PLL circuit for producing the read clock, and an automatic frequency control (AFC) circuit in a CRT deflection circuit, and in displaying pictures from such a video signal source as home VTRs, in which a great deal of jitter is included in the signal, the picture quality is deteriorated due to emphasized jitters caused by the variation of PLL characteristics.
Described above is the prior art method of displaying a picture from a standard video signal of 4:3 aspect ratio with a display unit with a 16:9 aspect ratio. This prior art method is based on the expansion of picture in the vertical direction so that the resulting picture is displayed in the entire screen area of 16:9 aspect ratio. However, it actually involves a problem of possibility in the loss of a crucial portion of a picture. Video signals of movie pictures as shown in FIG. 3F include a variety of sizes of picture field, and when these signals are simply rendered the vertical expansion, the literal field or other crucial section of picture is cut off or a blanking portion at the top or bottom of picture is left unremoved in many cases. Although the above-mentioned prior art of JP-A-3-11891 is devised for the vertical expansion mode to minimize the lost portion at the top and bottom of picture by switching the magnification factor between 4/3 and 5/4 for the first and second coefficient multipliers 413 and 414, it does not consider the horizontal expansion and compression of picture.
Moreover, in the case of displaying a picture from an input video signal by compression as shown in FIG. 3B, it is difficult to prevent the degradation of performance against jitters.
As techniques pertinent to the present invention, there are disclosed video signal processing circuits for enlarging a picture through interpolation for scanning lines by use of a field memory in U.S. Pat. Nos. 4,496,974 and 5,029,006.